The present invention relates to a method of forming an array of semiconductor nonvolatile memory cells on a semiconductor substrate, together with strap regions to make electrical contacts with memory cells, and a peripheral region for containing logic devices relating to the operation of the memory cell array.
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, self alignment minimizes the number of masking steps necessary to form memory cell structures, and enhances the ability to scale such structures down to smaller dimensions.
In the manufacture of memory cell arrays, it is also known to form cell elements that extend across the entire array of memory cells. For example, with an array having interlaced columns of isolation and active regions, with a plurality of memory cells in each active region, memory cell elements such as control gates, source regions, drain regions etc. can be formed to continuously extend across an entire row or column of memory cells. In order to ensure an equalized voltage on such elements for all the memory cells in the target row/column, strap regions have been used to provide multiple electrical connections along the length of continuously formed memory cell elements, so that uniform voltages are applied to all the memory cells in the affected row/column.
FIG. 1 illustrates a known strap region design. Strap region 1 is formed along side a memory cell array 2. The memory cell array 2 includes columns of active regions 3 interlaced with columns of isolation regions 4. Rows of memory cell pairs 5 are formed with word lines 6 and source lines 7 extending along the memory cell rows, with each pair of memory cells having two word lines 6 and sharing a single source line 7. (Those of skill in the art will recognize that the term source and drain may be interchanged. Further, the word line is connected to the control gate of the floating gate memory cell. Thus, the term control gate or control gate line may also be used interchangeably with the term word line). Typically, the word line and the source lines are made of polysilicon or polysilicide or salicide material. Thus, pure metal lines are used to strap these lines. Strap cells 8 are formed on the control gates 6 and source lines 7 as they traverse the strap region 1. Electrical contacts 9a and 9b are then formed onto the control gate (word) lines 6 and source lines 7 respectively by metal lines (not shown) traversing in the word line direction positioned above the array shown in FIG. 1 and electrically insulated therefrom for supplying the desired voltages to the various rows of control gates 6 and source lines 7.
Ideally, for larger memory arrays, a plurality of strap regions are interlaced within the memory cell array (e.g. one strap region for every 128 cells in the word line direction). Preferably, the strap regions are formed simultaneously with the process steps used to make the memory cell array.
As device geometries get smaller, it is increasingly difficult to reliably form electrical connections to the strap regions 8. The word lines 6 are very close to the source lines 7, and get even closer with smaller device geometries. As the distance between the control gate lines 6 and source line 7 shrinks, it becomes more difficult to form contacts 9a and 9b properly. For example, just a small shift of one of the control gate line 6 contacts toward an adjacent source line 7 would result in the contact being formed over both a word line 6 and a source line 7, thus shorting the two together. Further, there is simply no room to enlarge and separate the strap cells to increase the tolerance of the contact formation steps.
One or more logic or peripheral regions are also formed on the substrate as the memory cells and strap regions are formed. Peripheral regions are typically formed adjacent to the memory cell array on the same silicon substrate. Logic devices (i.e. MOS FET""s, etc.) are formed in these regions to operate the memory cell array or perform logic functions related to the memory cell array. In order to form such logic devices along side the memory cell array, the memory cells, the logic devices and the strap regions are formed using some of the same processing steps. For example, certain elements, such as poly layers for logic devices and memory cells, are often formed with the same processing steps, thus coupling the formation of these elements together. This can make it difficult to optimize elements of the logic devices without adversely affecting elements of the memory cells, and vice versa. Further, relatively simple manufacturing steps used to alter the structure in one region of the overall structure can be complicated by the existence of other structures in other regions. For example, CMP (chemical-mechanical polishing) is a well known technique for planarizing all the elements of a particular structure. However, if there are significant topography height differences between adjacent regions of the structure, a xe2x80x9cdishing effectxe2x80x9d occurs where the polishing pad of the CMP process actually over-polishes the lower portion(s) of the structure. Therefore, methods of forming non-volatile memory devices have avoided significant topography height differences preceding any CMP process. While it is known to form a pattern of dummy material for CMP processes used to form isolation regions for integrated circuit devices, it is unknown to use dummy material in the formation of the non-volatile memory cell elements such as the wordline.
Thus, there is a need for a manufacturing method that efficiently forms the memory cells, the logic devices and the strap cells using the same processing steps. Further, there is a need to form a logic/peripheral region adjacent the memory cell array where the logic poly gates are not coupled with those in the memory cells.
The present invention provides an improved memory cell, logic device and strap cell fabrication method that enhances chemical-mechanical planarization and provides for logic devices formed in a decoupled manner.
The present invention is a method of forming a memory device on a semiconductor substrate that has a memory cell array region for containing an array of memory cells and a peripheral region for containing logic devices. The method comprising the steps of forming a plurality of floating gates of a conductive material that are disposed over and insulated from the memory cell array region of the semiconductor substrate, forming a first insulation material over the floating gates, forming a first conductive material over the semiconductor substrate having first portions disposed over the first insulation material, second portions each disposed laterally adjacent to and insulated from one of the floating gates, and a third portion disposed over and insulated from a peripheral region of the substrate, forming a second insulation material over the first conductive material having first, second and third portions disposed over the first conductive layer first, second and third portions respectively, forming patterned dummy material over the second insulation material third portion, applying a chemical-mechanical polishing process to remove the first portions of the second insulation material and the first conductive material, the patterned dummy material, and top portions of the first insulation material, of the first conductive material second portions and of second insulation material second and third portions (where the first insulation material, the first conductive material second portions and the second insulation material second portions are all left with top surface portions that are exposed and substantially co-planar with each other), and forming a plurality of first and second regions in the substrate each having a conductivity type different from that of a portion of the substrate adjacent thereto, wherein each of the second regions is spaced apart from the first regions.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.